Hitachi HD6301V1

aus Schachcomputer.info Wiki, der freien Schachcomputer-Wissensdatenbank
(Weitergeleitet von 6301)
Zur Navigation springen Zur Suche springen

The HD6301V1 is an 8-bit CMOS single-chip microcomputer unit, Object Code compatible witk the HD6801. 4 KB ROM, 128 byte RAM, Serial Communication Interface (SCI), parallel I/O ports and muli function timer are incorporated in the HD6301V1. It is bus compatible with HMCS6800. Execution time of key instrucions are improved and serveral new instructions are added to increase system throughput. The HD6301V1 can be expanded up to 65Kk bytes. Like the HMCS6800 family, I/O level is TTL compatible with +5.0V single power supply. As HD6301V1 is fabricated by the advanced CMOS process technology, power dissipation is extremely reduced. In addition to that, HD6301V1 has Sleep Mode and Standby Mode at lower power dissipation mode. Therefore flexible low power consumption application is possible.

Features:

  • Object Code Upward Compatible witk HD6801 Family
  • Abundant On-Chip Functions Compatible with HD6801V0
    • 4 KB ROM, 128 Byte RAM, 29 Parallel I/O Lines, 2 Lines of Data Strobe, 16-bit Timer, Serial Communication Interface
  • Low Power Consumption Mode: Sleep Mode, Standby Mode
  • Minimum Instruction Execution Time
  • Bit Manipulation, Bit Test Instruction
  • Protection from System Upset: Address Trap, On-Code Trap
  • Up to 65k Words Address Space
  • Wide Operation Range
    • Vcc= 3 to 6V (f=0.1 ~0.5 MHz)
    • f=0.1 to 2.0 MHz (Vcc=5V ± 10%)
  • Type of Products:
Type No. Bus Timing
HD6301V1 1 MHz
HD63A01V1 1.5 MHz
HD63B01V1 2 MHz