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AT32F415

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ARM-based 32-bit Cortex-M4 MCU with 64 to 256 KB Flash, sLib, 11 timers, 1 ADC, 2 CMP, 12 communication interfaces (OTGFS, CAN)

Features

  • Core: ARM® 32-bit Cortex®-M4 CPU
    • 150 MHz maximum frequency, with a memory protection unit (MPU)
    • Single-cycle multiplication and hardware division
    • DSP instructions
  • Memories
    • 64 to 256 Kbytes of internal Flash memory
    • 18 Kbytes of boot code area used as a Bootloader
    • sLib: configurable part of main Flash set as a library area with code executable but secured, non-readable
    • 32 Kbytes of SRAM
  • Power control (PWC)
    • 2.6 to 3.6 V supply
    • Power on reset (POR), low voltage reset (LVR), and power voltage monitoring (PVM)
    • Low power modes: Sleep, Deepsleep, and Standby modes
    • VBAT for LEXT, ERTC and 20 x 32-bit battery powered registers (BPR)
  • Clock and reset management (CRM)
    • 4 to 25 MHz crystal (HEXT)
    • 48 MHz internal factory-trimmed high speed clock (HICK), 1 % accuracy at TA = 25 °C and 2 % accuracy at TA = -40 to +105 °C
    • PLL flexible 31 to 500 multiplication and 1 to 15 division factor
    • 32 kHz crystal (LEXT)
    • Low speed internal clock (LICK)
  • Analog
    • 1 x 12-bit 2 MSPS A/D converter, up to 16 input channels
    • Temperature sensor (VTS) and internal reference voltage (VINTRV)
    • 2 x comparators (CMP)
  • DMA: two 7-channel DMA controllers
  • Up to 55 fast GPIOs
    • All mappable on 16 external interrupts (EXINT)
    • Almost all 5 V-tolerant
  • Up to 11 timers (TMR)
    • 1 x 16-bit 7-channel advanced timer, 3 pairs of complementray channel PWM outputs with dead-time generator and emergency stop
    • Up to 5 x 16-bit and 2 x 32-bit timers, each with 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
    • 2 x watchdog timers (general WDT and windowed WWDT)
    • SysTick timer: a 24-bit downcounter
  • ERTC: enhanced RTC with auto-wakeup, alarm, subsecond accuracy, and hardware calendar; supports calibration
  • Up to 12 communication interfaces
    • 2 x I 2C interfaces for SMBus/PMBus support
    • 5 x USARTs, support master synchronous SPI and modem control, with ISO7816 interface, LIN and IrDA
    • 2 x SPIs (36 Mbit/s), both with I 2S interface multiplexed
    • CAN interface (2.0B Active), with 256 bytes of dedicated buffers
    • OTGFS interface with on-chip PHY, with 1280 bytes of dedicated buffers
    • SDIO interface
  • CRC calculation unit
  • 96-bit unique ID (UID)
  • Debug modes
    • Serial wire debug (SWD) and JTAG interfaces
  • Operating temperatures: -40 to +105 °C
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