HMCS45C

aus Schachcomputer.info Wiki, der freien Schachcomputer-Wissensdatenbank

The HMCS45C is the CMOS 4-bit single chip microcomputer which contains ROM, RAM, I/O and Timer/Event Counter on single chip. The HMCS45C is designed to perform efficient con¬troller function as well as arithmetic function for both binary and BCD data. The CMOS technology of the HMCS45C provides the flexibility of microcomputers for battery powered and battery back-up applications.

FEATURES

  • 4-bit Architecture
  • 2,048 Words of Program ROM (10 bits/Word) 128 Words of Pattern ROM (10 bits/Word)
  • 160 Digits of Data RAM (4 bits/Digit)
  • 44 I/O Lines and 2 External Interrupt Lines
  • Timer/Event Counter
  • Instruction Cycle Time: HMCS45C: 10μS HMCS45CL: 20 μs
  • All Instructions except One lnstruction; Single Word and Single Cycle
  • BCD Arithmetic Instructions
  • Pattern Generation Instruction — Table Look Up Capability —
  • Powerful Interrupt Function
    • 3 Interrupt Sources
      • 2 Extemal Interrupt Lines
      • Timer/Event Counter Multiple Interrupt Capability
  • Bit Manipulation Instructions for Both RAM and I/O
  • Option of I/O Configuration Selectable on Each Pin; Pull Up MOS or CMOS or Open Drain
  • Built-in Oscillator
  • Built-in Power-on Reset Circuit (HMCS45C only)
  • Low Operating Power Dissipation; 2mW typ.
  • Stand-by Mode (Halt Mode); 50 μW max.
  • CMOS Technology
  • Single Power Supply: HMCS45C: 5V±10% / HMCS45CL: 2.5V to 5.5V